Integrity and Reliability of Integrated CircuitS (IRIS), Phase III
DARPA is soliciting research proposals for a comprehensive exploration of the effects of extreme physical stresses on wear-out and aging mechanisms in CMOS FETs at 28nm and/or 14nm lithography node.
The objective of the IRIS Program Phase III is to explore aging effects in both transistors and transistor interconnects to create predictive models and to test how precisely and rapidly specific wear-out mechanisms can be asserted, for the purposes of accelerating burn-in, aging, and wear-out.
See the full DARPA-BAA-15-47 document attached.
The objective of the IRIS Program Phase III is to explore aging effects in both transistors and transistor interconnects to create predictive models and to test how precisely and rapidly specific wear-out mechanisms can be asserted, for the purposes of accelerating burn-in, aging, and wear-out.
See the full DARPA-BAA-15-47 document attached.
Agency: Department of Defense
Office: Defense Advanced Research Projects Agency
Estimated Funding: Not Available
Office: Defense Advanced Research Projects Agency
Estimated Funding: Not Available
Obtain Full Opportunity Text:
DARPA Solicitations Page
Additional Information of Eligibility:
Not Available
Full Opportunity Web Address:
http://www.darpa.mil/work-with-us/opportunities
Contact:
Mr. Kerry BernsteinProgram Manager
Agency Email Description:
MTO BAA Coordinator
Agency Email:
DARPA-BAA-15-47@darpa.mil
Date Posted:
2015-07-17
Application Due Date:
2015-09-04
Archive Date:
2016-03-04
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